Conventional high electron mobility transistors (HEMTs), also referred to as heterostructure FETs (HFETs) or modulation-doped FETs (MODFETs), are typically fabricated in GaN technology and generally characterized by a negative threshold voltage. That is, a current flows between source and drain terminals of the device even without applying any voltage to the gate electrode to open the transistor. Indeed, in GaN technology, a thin channel (inversion layer) is automatically created via strain and polarization effects between the source and drain terminals without the application of any voltage to the gate electrode. As such, the device is commonly referred to as being normally-on.
The normally-on feature of HEMTs is an intrinsic property of GaN technology, and restricts the range of applications for GaN technology to those applications where a power supply is available to generate the negative voltages necessary to turn off the GaN device. Moreover, the normally-on feature complicates the design of the circuitry needed to drive GaN transistors.
Attempts have been made to fabricate normally-off GaN HEMTs, i.e. GaN transistors with a positive threshold voltage. For example, a thin layer (20-50 nm) of p-type doped GaN material can be formed under the gate electrode. This thin p-type GaN layer depletes the inversion layer under the gate electrode, shifting the threshold voltage to positive values. The thin p-type GaN layer creates a vertical field which depletes and populates the naturally occurring inversion channel underlying the barrier layer, typically a layer of AlGaN. In addition, the vertical field generated by a voltage applied to the gate electrode allows to modulate on and off the inversion layer.
However, unlike conventional silicon technology, doping of a large bandgap material such as GaN is not trivial. Indeed, the fabrication of a thin p-type doped GaN layer requires very complicated processing. Moreover, threshold voltage instability can arise due to the non-uniform doping of the GaN layer and, in particular due to surface accumulation of p-type dopant elements at the exposed GaN surface. In addition, the maximum gate voltage which can be tolerated by the device is limited by the presence of a p-n junction under the gate electrode. Once the built-in voltage of the p-n junction is reached, a large and possibly detrimental gate leakage flows directly from the gate contact toward the source and drain electrodes. Using a p-type doped GaN layer under the gate electrode also limits the transconductance of the device because the gate electrode is spaced further away from the inversion channel by a distance corresponding to the thickness of the p-type GaN layer. The p-type doped GaN layer does yield a low threshold voltage of about 1V. In principle, the threshold voltage can be increased by increasing the thickness of the p-type GaN layer. However, the transconductance of the device degrades as a function of the p-type GaN layer thickness and the device becomes unusable if the thickness of this layer becomes too large.